In July 2026, Intel experienced a rare double boost that resonated across the market. Early in the month, the chip giant underwent a dramatic revaluation—HSBC analyst Frank Lee doubled Intel’s price target from $100 to $200. At the same time, research firm SemiAnalysis reported that Google’s next-generation TPU (codenamed Humufish) would abandon TSMC’s CoWoS advanced packaging in favor of Intel’s EMIB-T technology.
These two events are linked in a clear causal chain: Google’s order validates the technical feasibility and commercial value of Intel’s foundry business, while HSBC’s price target revision marks the first time the foundry segment is included in the valuation model. This is not a simple sentiment-driven rally—it’s a structural re-rating based on technological breakthroughs and business model validation.
EMIB-T: Intel’s Answer to CoWoS in Advanced Packaging
To appreciate the significance of Google’s order, it’s essential to understand where EMIB-T fits within the advanced packaging landscape.
Advanced packaging has become a core battleground in today’s semiconductor industry. TSMC’s CoWoS has long dominated the AI GPU and accelerator packaging market—NVIDIA’s Blackwell/B200, AMD’s MI300, and previous generations of Google’s TPU all rely on CoWoS-S capacity. CoWoS-S achieves high-density chip-to-chip interconnects using a large silicon interposer, but it’s limited by reticle size, supporting at most an interposer about 3.3 times the reticle area. As AI chip sizes continue to grow, CoWoS capacity has been in chronic short supply, creating a bottleneck across the AI supply chain.
Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology takes a different approach—it doesn’t lay a massive silicon interposer across the entire package. Instead, it embeds miniature silicon bridges only where chip-to-chip connections are needed. This design offers theoretical advantages in both material cost and design flexibility.
EMIB-T is the latest iteration of this technology. Compared to standard EMIB, the core upgrade in EMIB-T is the introduction of Through-Silicon Via (TSV) technology. Standard EMIB’s power delivery path is cantilevered, resulting in relatively high voltage drop. EMIB-T uses TSVs for vertical power delivery, allowing current to flow directly through the substrate to the chip, significantly shortening the power path and increasing power density. This improvement is especially critical for integrating high-bandwidth memory (HBM4/HBM4E).
In terms of performance, Intel claims EMIB-T will support composite die sizes of 8 to 10 times the reticle area by 2026. At ECTC 2026, Intel showcased further progress: first-layer interconnect bump pitch has shrunk to 25 microns, and package size has expanded to 120×120 mm. Compared to the 45-micron pitch used in Granite Rapids packaging, bump density has increased by 65%.
The Strategic Significance of Google’s Order: From Technical Validation to Commercial Endorsement
Google’s decision to adopt EMIB-T instead of sticking with CoWoS sends several important signals.
First, it serves as a direct endorsement of EMIB-T’s technical maturity. Google’s TPU is a critical in-house AI chip, with strict requirements for performance, power efficiency, and production timelines. Choosing a packaging technology that hasn’t yet seen large-scale production implies Google’s internal technical review gave it a high level of confidence.
Second, it reflects hyperscalers’ strong desire to diversify supply chain risk. In recent years, CoWoS capacity constraints have repeatedly delayed AI chip deliveries. For Google, establishing a second source for advanced packaging is not just about cost—it’s a strategic move to ensure supply chain security.
Third, this opens a key customer window for Intel’s foundry business. When HSBC’s Frank Lee first upgraded Intel to "Buy" in April, he didn’t include the foundry segment in his valuation due to insufficient external customer commitments. The Google order fills this gap. In his July report, Lee noted that collaborations with Apple, Google, NVIDIA, Microsoft, and Amazon are increasing, with design commitments potentially materializing in the second half of 2026.
However, as a next-generation packaging process, EMIB-T’s mass production yield stability and timeline remain to be proven. If there are significant delays, Google may still revert to TSMC’s CoWoS-L capacity as a backup. This remains a key variable Intel must continue to address.
HSBC’s $200 Price Target: Systematic Overhaul of Valuation Logic
Frank Lee’s $200 price target isn’t a simple, sentiment-driven hike—it’s built on a comprehensive overhaul of Intel’s valuation model.
Lee’s view on Intel has shifted dramatically over the past year: from a "Reduce" rating and $24 target at the end of 2025, to "Buy" at $95 in April 2026, and then doubling to $200 in July. The main driver of this shift is the foundry business moving from "zero valuation" to a "core valuation component."
Specifically, Lee’s model incorporates several key adjustments:
Upgraded server CPU shipment forecasts. HSBC raised its 2026 server CPU shipment growth forecast from 20% to 25%, and 2027 from 20% to 30%. Lee sees server CPUs as the "key growth driver" for Intel’s earnings over the next two years.
Higher average selling price (ASP) expectations. In a supply-constrained environment, Lee expects Intel to increase ASPs by 20% in 2026 and another 10% in 2027. These price hikes are projected to drive gross margins well above current market consensus.
Data center and AI revenue forecasts well above consensus. HSBC projects DCAI (Data Center & AI) revenue of $22.8 billion in 2026 and $29.1 billion in 2027—16% and 33% higher than Wall Street consensus, respectively.
Foundry business included in valuation for the first time. This is the most critical change. Lee’s April model excluded the foundry segment due to insufficient external customer commitments. The Google order changed that assessment.
Lee’s price target is an extreme outlier on Wall Street—TipRanks data shows the average analyst target for Intel is around $101. Such a wide deviation is rare for large-cap stocks. It either signals that the market will eventually move in this direction, or that some assumptions will be tested in future earnings reports.
Market Response and Risk Assessment Amid Multiple Positive Catalysts
On July 6 (UTC+8), Intel’s share price rally was not driven by HSBC’s price target alone. BlueFin Research Partners’ latest report confirmed that Intel has resolved yield fluctuations between wafers on its 18A process, with two fabs now delivering a combined monthly capacity of about 30,000 wafers. The process is now ready for sustainable large-scale production. The 18A node is Intel’s answer to TSMC’s 2nm process, and previous yield issues were one of the market’s biggest concerns.
As a result, Intel has delivered positive signals on three fronts: advanced process (18A yield issues resolved), advanced packaging (Google’s EMIB-T order), and foundry business (customer commitments materializing).
However, risks remain. Wall Street’s consensus rating on Intel is still "Hold"—in the past three months, there have been 11 Buys, 25 Holds, and 2 Sells. EMIB-T’s mass production yield still needs time to prove itself. The ramp-up schedule for large-scale 18A production is also not fully confirmed. Additionally, Intel’s share price has rebounded sharply from its lows over the past year, and there’s debate about whether the current valuation fully reflects these positives.
Conclusion
Google’s EMIB-T order and HSBC’s $200 price target both point to a core thesis: Intel’s foundry business is moving from "concept" to "verifiable commercial reality." This is not just a technological breakthrough—EMIB-T provides AI chips with a second advanced packaging path beyond CoWoS—but also a restructuring of the business model. For a company once seen as a "turnaround story," gaining technical validation from one of the world’s largest cloud providers and a re-rating from a top Wall Street analyst signals an industry logic worth watching closely.
For the crypto sector and broader risk asset markets, Intel’s re-rating offers a lens into shifting power structures within the semiconductor supply chain. As AI compute demand continues to surge, the competitive landscape for advanced packaging and process nodes is undergoing subtle yet profound changes.
FAQ
Q: What are the core technical differences between EMIB-T and TSMC’s CoWoS?
EMIB-T uses embedded miniature silicon bridges to connect chips, placing bridges only where interconnects are needed. CoWoS, on the other hand, uses a full-size silicon interposer. EMIB-T offers lower material costs, greater design flexibility, and leverages TSV technology for vertical power delivery. CoWoS-S supports up to about 3.3 times the reticle area, while Intel claims EMIB-T can reach 8 to 10 times.
Q: Why did HSBC double Intel’s price target from $100 to $200?
HSBC analyst Frank Lee included Intel’s foundry business in his valuation model for the first time, having previously excluded it due to a lack of external customer commitments. He also raised 2026 and 2027 server CPU shipment growth forecasts to 25% and 30%, respectively, and expects a 20% increase in average selling price in 2026. Lee’s 2027 DCAI revenue forecast is about 20% above Wall Street consensus.
Q: Why did Google switch from TSMC’s CoWoS to Intel’s EMIB-T?
Key drivers include diversifying supply chain risk, avoiding CoWoS’s persistent capacity bottlenecks, and seeking cost and design flexibility. Chronic CoWoS shortages have slowed AI chip deliveries. Establishing a second advanced packaging source is a strategic necessity for major cloud providers.
Q: What’s the latest on Intel’s 18A process?
BlueFin Research Partners reports that Intel has resolved wafer-to-wafer yield fluctuations on 18A, with two fabs now delivering a combined monthly capacity of about 30,000 wafers. The process is now ready for sustainable large-scale production. The enhanced 18A-P entered risk production in mid-June 2026. Previously, a May report from Morgan Stanley showed 18A yields at around 50%.
Q: What are the mass production risks for EMIB-T packaging technology?
EMIB-T is Intel’s latest generation packaging process, and it remains to be seen whether mass production yields and timelines can meet customer ramp schedules. If there are significant delays, customers may revert to TSMC’s CoWoS-L as a backup. Intel must continue to prove its execution in large-scale manufacturing through ongoing technical validation.
