CoWoS wafer average pricing breaks $10,000, advanced packaging becomes TSMC’s new profit engine

AI-driven waves are reshaping the semiconductor industry’s landscape. Advanced packaging technologies—once regarded as back-end processes—have now risen to become a key part of the AI chip supply chain. As TSMC’s CoWoS wafer average pricing has broken through $10k, comparable to 7nm advanced process technologies, the packaging and testing industry is shifting from “low-margin” competition toward a “high-value” competitive arena.

At the same time, Intel’s EMIB has quietly risen, and the competitive landscape for the advanced packaging market has begun to show subtle changes.

CoWoS is no longer just a back-end process; packaging technology pricing is being revalued

In the past, packaging was seen as a relatively lower value-added part of the chip manufacturing process. However, as AI chips’ requirements for computational density and memory bandwidth have rapidly surged, this perception has been completely overturned. Commercial Times (工商時報) points out that, through 2.5D and 3D packaging architectures, combining die stacking and heterogeneous integration technologies, advanced packaging is becoming a critical path for continuing Moore’s Law—directly determining the performance, power consumption, and system architecture of AI chips.

Market data provides even stronger proof of this pricing revaluation. Chip industry insiders revealed that the average selling price of a single CoWoS wafer is about $10,000, which is already comparable to 7nm advanced process technologies.

Meanwhile, advanced packaging does not rely on EUV lithography machines costing hundreds of millions of dollars, so capital expenditures are relatively lower. Coupled with Taiwanese makers’ equipment introductions such as Siliconware (3131), Shin-Etsu? (6640), and Wanrun (6187), a profit structure of “high price, low depreciation” is forming, and the gross margin potential is rapidly moving toward advanced process technologies.

TSMC’s business model changes; packaging’s revenue share keeps rising

The rise of advanced packaging is also fundamentally changing TSMC’s business model. In 2025, advanced packaging accounted for about one-tenth of TSMC’s total revenue, and this figure is rising as AI chip demand continues to grow. TSMC’s positioning is gradually shifting from the traditional “foundry services” toward “system-level integration services,” with the strategic value of the packaging segment significantly amplified.

The speed of capacity expansion better reflects market confidence. Legal-person forecasts estimate that TSMC’s advanced packaging capacity will reach about 1.3 million units in 2026, and challenge 2.0 million units in 2027, with the supply side fully working to catch up to the demand shortfall.

In terms of technology layout, TSMC is also actively advancing SoIC 3D stacking and the COUPE silicon photonics integration platform. By using optoelectronic co-packaging (CPO) to integrate computing and optical communications within the same packaging architecture, it further reduces power consumption and improves transmission efficiency.

Intel EMIB rises—what are analysts saying about competition in the packaging landscape?

Meanwhile, Citrini analyst Jukan recently posted on the social platform X, revealing that a large number of senior engineers are reportedly joining Intel’s EMIB advanced packaging team, with expectations that EMIB can capture a certain scale of market share.

User @christophauto also mentioned in a reply the current expansion bottleneck for CoWoS. They pointed out that CoWoS uses a large-area silicon interposer; when expanding the photomask size, the difficulty and cost of photomask stitching (reticle stitching) will quickly rise, impacting yield. The area of the silicon interposer would also increase the risk of warpage (warpage) after scaling up. At the same time, cutting a circular wafer to form a rectangular interposer inherently involves a hard-to-avoid problem of area waste.

In comparison, EMIB eliminates the large-area silicon interposer by using small silicon bridges embedded in an organic substrate, offering higher flexibility. Once a glass substrate is adopted, thermal stability is further improved, making its cost competitiveness even more prominent.

However, the drawback is that the silicon bridge area and wiring density limitations of EMIB restrict interconnect bandwidth. Transmission distances are longer and latency is slightly higher than CoWoS—making it a major issue for GPU vendors with extremely demanding bandwidth requirements. In addition, TSMC is also actively developing CoPoS (panel-level packaging) technology. By replacing rectangular panels with circular wafers, it directly resolves the limitations of photomask stitching and wafer wastage. It is expected to enter mass production as early as 2028 to 2029.

(Chen Liwu sealed in glory! Citrini’s praise of Intel “this year’s most outstanding financial report,” hoping to inherit TSMC’s CoWoS spillover demand)

Competition and collaboration proceed in parallel; CoWoS’ pedestal is unlikely to be shaken in the short term

In terms of competitive relationships at the application level, CoWoS is more welcomed by AI training scenarios with high bandwidth demands—such as Nvidia Blackwell and deep binding with the next-generation Rubin architecture. EMIB, on the other hand, with its cost advantages and large-size packaging flexibility, is gradually gaining a foothold in the inference and cloud players’ self-developed ASIC market, such as Google’s plan to introduce TPU v9 in 2027.

However, between TSMC’s CoWoS and Intel’s EMIB, it is not simply a competitive relationship. During TSMC’s earlier earnings calls, TSMC disclosed that it would open up computing chips for Intel to use with EMIB packaging, forming a complementary division of labor between upstream and downstream.

This competition in advanced packaging is, in essence, a process of tiered market maturity. The top-tier GPU training scenarios are led by CoWoS, while inference and the ASIC market are targeted by EMIB. TSMC’s throne remains stable in the short term, but the reshaping of the packaging map is just beginning.

This article, “CoWoS average wafer pricing breaks $10,000; advanced packaging becomes TSMC’s new profit engine,” first appeared on Lianxin ABMedia.