Taiwanese chip designer MediaTek appointed former Taiwan Semiconductor Manufacturing Co (TSMC) executive Douglas Yu as a part-time adviser on May 4, according to Reuters. The move supports MediaTek’s expansion into the AI chip market and its advancement of packaging technology.
Yu previously held an executive role at TSMC, where he helped develop advanced packaging technologies including CoWoS (Chip on Wafer on Substrate), which combines multiple chip parts into a single package. CoWoS is widely used in AI chips, including Nvidia products.
MediaTek’s appointment of Yu aligns with the company’s plan to generate several billion dollars in revenue from AI accelerator application-specific integrated circuit (ASIC) chips by 2027. Yu’s background in advanced packaging addresses a key design challenge: TSMC’s CoWoS roadmap indicates that future CoWoS system-in-package products could exceed 14 reticle sizes by 2029, which raises heat and cooling demands for larger packages.
Across the chip industry, advanced packaging now plays a larger role in performance and efficiency as gains from transistor-density scaling slow. According to TSMC’s CoWoS roadmap, by 2029, larger packages could support significantly more compute transistors and memory bandwidth compared to 2024 reference designs—projecting 48 times more compute transistors and 34 times more bandwidth under TSMC’s roadmap assumptions.
This shift is reshaping semiconductor competition. Chip companies now must manage the physics of large multi-die systems, including heat management, power delivery, and signal integrity—the reliability of electrical signals moving through the system.
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